QSIM
5.2 FUTURE WORKS ON QSIM
In QSIM, one of our major tasks was to design an in-built Assembler that will convert all Queue Assembly program into machine code before storing them in memory. We could not accomplish this due to time constraints. However, there already exists developed Queue Core Assembler for the Queue Core Processor. This was developed in C-programming language. Integrating this with our QSIM was quite uneasy due to difference in language platforms. Future works could possibly look into this integration.
We could not also design the Memory module for QSIM due to the absence of the Assembler for QSIM. It was expected that the designed Memory will store all assembled instructions before program execution. Future development of QSIM Assembler will therefore necessitate the design of the QSIM Memory module.
More importantly, QSIM will require Data and Text segments that will show the content of the Data and Text Segments of the QSIM Memory. Visualization in the QSIM GUI will be required to show this to the user.
In QSIM, we have designed Registers Components to store integer and floating point intermediate values for Queue Computation. For now, only the Queue Registers have been implemented to handle integer computation. Future works should look into the implementation of the floating point registers for the QSIM.
Some components were added to QSIM but were not implemented due to the absence of QSIM assembler and Memory module. This includes the Speed panel that the user could use to specify how fast or slow execution should be done. The Step Forward, Back Step, Stop and Reset are menu and tool bar components designed for future use when the Memory and Assembler components are incorporated. Only the Run button on the menu or tool bar item has been implemented to execute QSIM programs.
QSIM execute only one instruction at a time. For maximum parallelism, pipeline stages of the Queue Core Processor need to be implemented. Naturally, Queue Core Processor executes four (4) instructions per cycle. Future works should seek this implementation.
REFERENCES
[1]. M. Sowa, B. Abderazek, T. Yoshinaga, Parallel Queue Processor Architecture Based on Produced order Computation Model, The Journal of Supercomputing, Volume 32, Issue 3, 2005, pp. 217-229
[2]. B. Abderazek, S. Kawata, M. Sowa, Design and Architecture for an Embedded 32-bit QueueCore, Journal of Embedded Computing,Vol. 2, No. 2, pp 191-205, 2006
[3]. A. Ben Abdallah, A. Canedo, T. Yoshinaga, and M. Sowa: The QC-2 Parallel Queue Processor Architecture, Journal of Parallel and Distributed Computing, Vol. 68, No. 2, pp.235-245, 2008.
[4]. A. Canedo, B. Abderazek, and M. Sowa: A GCC based Compiler for the Queue Register Processor, Proceedings of International Workshop on Modern Science and Technology, pp. 250-255, May 2006.
[5]. Ben A. Abderazek, Masashi Masuda, Arquimedes Canedo, Natural Instruction Level Parallelism-aware Compiler for High-Performance QueueCore Processor Architecture Adaptive Systems Laboratory, University of Aizu, Japan
[6]. H. Hoshino, A. Ben Abdallah and K. Kuroda: Advanced Optimization and Design Issues of a 32- bit Embedded Processor Based on Produced Order Queue Computation Model, IEEE/IFIP International Conference on Embedded and Ubiquitous Computing EUC2008, pp. 16-22, Dec.
2008.
[7]. Canedo, A., Code Generation Algorithms for Consumed and Produced Order Queue Machines. Master‟s thesis, University of Electro-Communications, Tokyo, Japan (September 2006).
[8]. S. Okamoto. Design of a Superscalar Processor Based on Queue Machine Computation Model, In IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, pages 151-154, 1999.
[9]. A. Canedo, B. Abderazek, M. Sowa, A new code generation algorithm for 2-offset producer order queue computation model, Graduate School of Information Systems, University of Electro-Communications, Japan
[10]. A. Canedo, B. Abderazek, M. Sowa, An Efficient Code Generation Algorithm for Code Size Reduction using 1-offset P-Code Queue Computation Model, Graduate School of Information Systems, University of Electro-Communications, Japan
[11]. Canedo, Ben Abderazek, and Masahiro Sowa, Compiler Support for Code Size Reduction using a Queue-based Processor Arquimedes Graduate School of Information Systems, University of Electro-Communications, Japan
[12]. Ben A. Abderazek, QC1 Processing Stages Algorithms Technical Report, TRQC1PSA03, October 3rd, 2003
[13]. ASL-Ben Abdallah Group, Qasm Technical Report, Ref. TR12010, University of Aizu
[14]. Hiroki Hoshino, QC-2 Data Path Version 2.0, Adaptive Systems Laboratory, University of Aizu, October 2009
[15]. Abderazek Ben Abdallah, Technical report QC2MY07, University of Electro-communications Graduate School of Information Systems, May 2007
[16]. Ben A. Abderazek; Queue Core Instruction set architecture, January 2003
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[32]. B. Preiss and C. Hamacher, Data Flow on Queue Machines. In 12th Int. IEEE Symposium on computer Architecture, pages 342-351, 1987.
[33]. Gary S, Mikhail S. Edward S., Evaluating the use of Register Queues in Software Pipelined Loops, Advanced Computer Architecture Lab, University of Michigan
[34]. Schmitt H., Benjamin L., Benjamin, Y., Queue Machines, Hardware Compilation in Hardware, Carnegie Mellon University.
[35]. Fernandes, Marcio M, A Clustered VLIW Architecture Based on Queue Register Files, school of informatics, College of Engineering, University of Edinburgh, 1998
[36]. S. Okamoto, H. Suzuki, A. Maeda and M. Sowa, Design of a Superscalar Processor Based on Queue Machine Computation Model: IEEE PACRIM, 1999, pp. 22-24.
[37]. B. A. Abderazek, N. Kirilka, and M. Sowa: FARM queue Mode: On a Practical Queue Execution model, Proceedings of the Int. Conf. on Circuits and Systems, Computers and Communications, Tokushima, Japan, 2001, pp. 939-944.
[38]. H. Suzuki, O. Shusuke, A. Maeda and M. Sowa, Implementation and evaluation of a Superscalar, Processor Based on Queue Machine Computation Model, IPSJ SIG, 99(21), 1999, 91-96.
[39]. M. Sowa, “Queue Processor Instruction Set Design”, the University of Electro Communications, Sowa laboratory, Technical Report SLL97301, 1997.
[40]. M. Sowa, B. A. Abderazek, S. Shigeta, K. Nikolova, and T. Yoshinaga, " Proposal and Design of a Parallel Queue Processor Architecture (PQP) ", 14th IASTED Int. Conf. on Parallel and Distributed Computing and System, Cambridge, USA, Nov. 2002, pp. 554-560.
[41]. B.A. Abderazek, M. Arsenji, S. Shigeta, T. Yoshinaga, M. Sowa, Queue Processor for novel queue computing paradigm based on produced order scheme, in: HPC2004, International Conference on High Performance Computing, Tokyo, July 2004, pp. 169–177.
[42]. B.A. Abderazek, Dynamic instructions issue algorithm and a queue execution model toward the design of hybrid Processor architecture, Ph.D. Thesis, Graduate School of Information Systems, the University of Electro-Communications, 2002.
[43] Object Management Group (OMG), Unified Modeling Language Specification, Version 2.1.1, (2007-02-07).
[44] Booch, G., Object Oriented Design with Applications, Benjamin/Cummings, Redwood, California, 1991. ISBN: 0-8053-0091-0, ISSN: 0896-8438
[45] Coad, P., and E. Youdon, Object-Oriented Analysis, Prentice Hall, Eaglewood Cliffs, New Jersey, 1991. ISBN: 0-13-630070-7
[46] http:// course.missouristate.edu/kenVollmar/MARS/index.htm
[47] http:// pages.cs.wisc.edu/~larus/spim.html
APPENDIX I
INSTRUCTION SET ARCHITECTURE FOR QC-2 PROCESSOR
The QC-2 Processor implements a produced order instruction set architecture. Here, each instruction can encode at most 2 operands that specify the location in the register file where to read the operands. The Processor determines the physical location of operands by adding the offset reference in the instruction to the current QH pointer.
All instructions of QC-2 Processor are 16-bit wide, allowing simple fetch and decode stages and facilitating pipelining of the Processor. In the case of insufficient bit to express large constants, memory offsets or offset references, the QueueCore Processor implements the QCaEXT which inserts a “covop” instruction. This special instruction is used to extend load and store instructions offsets and also extends immediate values when necessary. This consequently curbs the bit- width constraints in the QueueCore Processor.
INSTRUCTION FORMAT AND ENCODING FOR THE QC-2 ARCHITECTURE
QC-2 has a fixed instruction length format where each instruction has a fixed length of 16-bit wide. This obviates the need for instruction length checking in the decode stage hence enhancing instruction processing performance in the QC-2 Processor.
INSTRUCTION FORMAT
QC-2 instruction set architecture uses mnemonics to denote operations. Each operation has a unique operation code (opcode). The instruction format for some of selected operations of the QC-2 instruction set is given below:
INSTRUCTION FORMAT FOR COVOP INSTRUCTION
Description: Convey an 8-bit address to a load or store instruction to extend the addressing bits from 8 to 16 bits. Here, QH = 0 & QT = 0
INSTRUCTION FORMAT FOR LOAD / STORE INSTRUCTION
8 bits 8 bits
covop: 00000100 Addr 1
Mnemonic Action QH QT Binary
Covop addr1 Convey address 0 0 00000100
15 8 7 0
6 -bits 2 -bits 8-bits
Load :opcode d addr 0
Mnemonic Action QH QT Binary
Ldk addr0(d) QTw m((d)+addr1.addr0) 0 1 opcode 15 10 9 8 7 0
LOAD INSTRUCTION: Ld k: k=byte, string, word (k could be unsigned or signed)
Description: the above instruction load K (byte, string or word-signed/unsigned) to the operand queue pointed by the QT from memory address ((d)+addr0) or((d)+addr1.addr0).
Description: the above instruction store K (byte, string or word-signed/unsigned) to the operand queue pointed by the memory address ((d) +addr0) or ((d) +addr1.addr0) from the Queue Head (QH).
INSTRUCTION FORMAT FOR IMMEDIATE INSTRUCTION
STORE INSTRUCTION: st k: k=byte, string, word (k could be unsigned or signed)
Load :opcode d addr 0
Mnemonic Action QH QT Binary
St k addr0(d) QHw m((d)+addr1.addr0) 1 0 opcode 15 10 9 8 7 0
8 bits 8 bits
LOAD IMMEDIATE: Ldi k: k=value or address
Load :opcode value
Mnemonic Action QH QT Binary
Ldi k value QTw (value)/(address of inst+value) 1 0 opcode 15 8 7 0
Description: the above instruction load K (immediate value or address) to the operand queue pointed by the QT from memory address ((d) +addr0) or ((d) +addr1.addr0). When k=address, PQPcfo and PQPcf+ are set to yes.
INSTRUCTION FORMAT FOR CONTROL INSTRUCTIONS BRANCH INSTRUCTION
Description: This instruction to target the operand queue pointed by the program counter ((pc+t) or (pc+addr1.t)) to FC. CC refers to the condition code.
K=eq: branch equal (be) k=ge: branch greater or equal (bge) K=ne: branch not equal (bne) k=le: branch less or equal (ble) k=lt: branch less than (blt) b t: branch target
k=gt: branch greater than (bgt)
8 bits 8 bits
BRANCH TARGET/ BRANCH K TARGET: b t/ b k t: k=eq, ne, lt, gt, le, ge
b/b k :opcode t
Mnemonic Action QH QT Binary
b t/ b k t FC pc+2(addr1.t) , if cc= k or Ø 0 0 opcode 15 8 7 0
QUEUE CONTROL INSTRUCTIONS FORMAT
STOP QH/LQH MOVE
Description: This instruction stops QH/LQH move to target the operand queue pointed that the QH/LQH stop to move from nth position.
FIXED QH AND LQH AUTOMATICALLY
8 bits 8 bits
STOP QH/LQH MOVE: stpqh /stplqh n
Stpqh/ stplqh :opcode n
Mnemonic Action QH QT Binary
stpqh/stplqh n Stop QH/LQH moving QH=9; LQH=0 0 opcode
15 8 7 0
AUTO FIXED QH/ LQH: autqh /autlqh n
autqh / autlqh :opcode n
Mnemonic Action QH QT Binary
autqh/autlqh n Fixed QH/LQH automatically QH=9; LQH=0 0 opcode 15 8 7 0
Description: This instruction to target the operand queue pointed that the QH/LQH will be fixed in the nth position
INSTRUCTION FORMAT FOR JUMP/ CALL
Description: This instruction to target the operand queue pointed by the memory address ((a) +t) or ((a) +2(addr1.t)) to FC. „(a)‟: refers to the content of register „a‟.
INSTRUCTION FORMAT FOR BARRIER / INTERRUPT
The following instructions use the above instruction format:
Return from call (rfc), return from interrupt (rfi), no operation (nop), stop (halt), barrier (bar)
6 -bits 2 -bits 8-bits
JUMP/ CALL TARGET: jump/ call t(a)
Jump/call: opcode a t
Mnemonic Action QH QT Binary
Jump/call t(a) FC (a)+2(addr1) 0 0 opcode 15 10 9 8 7 0
8 bits 0
SHIFT INSTRUCTION FORMAT
ROTATE INSTRUCTION FORMAT
DUPLICATE/ MOVE INSTRUCTION FORMAT
8-bits 4 -bits 4-bits
8 -bits 8-bits
8 -bits 8-bits
ALU INSTRUCTION FORMAT FOR SINGLE WORD
Description: This instruction performs the operation on two single operands to the operand queue pointed by QT from (qhw0 op (qh+n) w). Here, „op‟ refer to the specified operator (+, - , * , /etc).
ALU INSTRUCTION FORMAT FOR DOUBLE WORD
The instruction format for double is similar to that for single word except that each operation is double word instead of single. Each operation is appended with d (double)
8 -bits 8-bits
Opcode Offset(n)
OPERATION n: operation (add, addu, sub, subu, subo, subuo, mul, mulu, div, divu, divo, mod)
Operation: opcode n
Mnemonic Action QH QT Binary
Operation n qtw0 qhw0 op (qh+n) w 1 1 opcode 15 8 7 0
OPERATION d n: operation (addd, adddu, subd, subdu, subdo, subduo, muld, muldu, divd, divdu, divdo, modd)
Operation: opcode n
Mnemonic Action QH QT Binary
Operation n qtd0 qhd0 op (qh+n) d 2 2 opcode
15 8 7 0
Description: These instructions perform operation on two double operands to the operand queue pointed by the QT from (qhd0 op (qh+n) d).
APPENDIX II
QUEUE CORE ASSEMBLER AND RUNTIME SIMULATOR SOURCE CODES The selected source codes are provided according to packages.
QSIM .REGISTERS PACKAGE Qregister.JAVA CLASS
package qsim.registers;
import java.util.Observable;
/**Class for the Queue Register Object */
public class QRegister extends Observable{
private int index,resetValue;
private String name;
private volatile int value;
/**constructor for new Queue register */
public QRegister(int index,int value){
this.index=index;
this.value=value;
this.resetValue=value;
}
/**constructor for new Floating point register */
public QRegister(String name, int value){
this.name=name;
this.value=value;
this.resetValue=value;
}
/******************************************/
/**getter methods for QRegister variables**/
/******************************************/
/**get index of a QRegister*/
public int getIndex(){
return index;
}
/** Return the name of the Floating point Register*/
public String getName(){
return name;
}
/** Returns the value of the QRegister. Observers are notified of the READ operation.
@return value The value of the QRegister.
*/
public synchronized int getValue(){
notifyAnyObservers(AccessNotice.READ);
return value;
}
/** Returns the value of the QRegister. Observers are not notified * @return value The value of the QRegister.*/
public synchronized int getValueNoNotify(){
return value;
}
/** Returns the reset value of the QRegister.
* @return The reset (initial) value of the QRegister.
public int getResetValue(){
return resetValue;
}
/** Sets the value of the QRegister to the val passed to it.
* Observers are notified of the WRITE operation.
* @param val Value to set the QRegister to.
* @return previous value of Qregister*/
public synchronized int setValue(int val){
int old = value;
value = val;
notifyAnyObservers(AccessNotice.WRITE);
return old;
}
/** Resets the value of the QRegister to the value it was constructed with. Observers are not notified.*/
public synchronized void resetValue(){
value = resetValue;
}
/** Change the QRegister's reset value; the value to which it will be * set when (resetValue()) is called */
public synchronized void changeResetValue(int reset) { resetValue = reset;
}
/** Method to notify any observers of register operation that has just occurred.*/
private void notifyAnyObservers(int type) { if (this.countObservers() > 0){
this.setChanged();
this.notifyObservers(new QRegisterAccessNotice(type, this.index));
} }
}
QregisterFile.JAVA CLASS package qsim.registers;
import java.util.Observer;
import javax.swing.JOptionPane;
import qsim.Globals;
import qsim.gui.QRegisterSegmentForAlu;
import qsim.gui.QRegisterSegmentForLoad;
import qsim.gui.QsimResultsPane;
/** Class to create the Queue Registers */
public class QRegisterFile {
public static final int STACK_POINTER_REGISTER = 0;
private static int QH=0;
private static int QT=0;
private static int CN=0;
private static int PN=0;
private static int qSize=0;
private int qMaxSize=256;
QsimResultsPane messagePane=new QsimResultsPane ();
/** creating the Queue register with initial values */
private static QRegister []qReg={
new QRegister(0,0),new QRegister(1,0), new QRegister(2,0),new QRegister(3,0), new QRegister(4,0),new QRegister(5,0), new QRegister(6,0),new QRegister(7,0), new QRegister(8,0),new QRegister(9,0), new QRegister(10,0),new QRegister(11,0), new QRegister(12,0),new QRegister(13,0), new QRegister(14,0),new QRegister(15,0),
new QRegister(16,0),new QRegister(17,0), new QRegister(18,0),new QRegister(19,0), new QRegister(20,0),new QRegister(21,0), new QRegister(22,0),new QRegister(23,0), new QRegister(24,0),new QRegister(25,0), new QRegister(26,0),new QRegister(27,0), new QRegister(28,0),new QRegister(29,0), new QRegister(30,0),new QRegister(31,0), new QRegister(32,0),new QRegister(33,0), new QRegister(34,0),new QRegister(35,0), new QRegister(36,0),new QRegister(37,0), new QRegister(38,0),new QRegister(39,0), new QRegister(40,0),new QRegister(41,0), new QRegister(42,0),new QRegister(43,0), new QRegister(44,0),new QRegister(45,0), new QRegister(46,0),new QRegister(47,0), new QRegister(48,0),new QRegister(49,0), new QRegister(50,0),new QRegister(51,0), new QRegister(52,0),new QRegister(53,0), new QRegister(54,0),new QRegister(55,0), new QRegister(56,0),new QRegister(57,0), new QRegister(58,0),new QRegister(59,0), new QRegister(60,0),new QRegister(61,0), new QRegister(62,0),new QRegister(63,0), new QRegister(64,0),new QRegister(65,0), new QRegister(66,0),new QRegister(67,0), new QRegister(68,0),new QRegister(69,0), new QRegister(70,0),new QRegister(71,0), new QRegister(72,0),new QRegister(73,0), new QRegister(74,0),new QRegister(75,0), new QRegister(76,0),new QRegister(77,0),
new QRegister(78,0),new QRegister(79,0), new QRegister(80,0),new QRegister(81,0), new QRegister(82,0),new QRegister(83,0), new QRegister(84,0),new QRegister(85,0), new QRegister(86,0),new QRegister(87,0), new QRegister(88,0),new QRegister(89,0), new QRegister(90,0),new QRegister(91,0), new QRegister(92,0),new QRegister(93,0), new QRegister(94,0),new QRegister(95,0), new QRegister(96,0),new QRegister(97,0), new QRegister(98,0),new QRegister(99,0), new QRegister(100,0),new QRegister(101,0), new QRegister(102,0),new QRegister(103,0), new QRegister(104,0),new QRegister(105,0), new QRegister(106,0),new QRegister(107,0), new QRegister(108,0),new QRegister(109,0), new QRegister(110,0),new QRegister(111,0), new QRegister(112,0),new QRegister(113,0), new QRegister(114,0),new QRegister(115,0), new QRegister(116,0),new QRegister(117,0), new QRegister(118,0),new QRegister(119,0), new QRegister(120,0),new QRegister(121,0), new QRegister(122,0),new QRegister(123,0), new QRegister(124,0),new QRegister(125,0), new QRegister(126,0),new QRegister(127,0), };
/** method to show the content of the QRegisters */
public static void showQReg(){
Globals.getGui().getMainPane().getQRegisterDynamicsPane().getaluSegmentWindow();
QRegisterSegmentForAlu.getAluQreg().append("***********************\n");
QRegisterSegmentForAlu.getAluQreg().append("QUEUE REGISTER CONTENT AFTER ALU OPERATION \n");
QRegisterSegmentForAlu.getAluQreg().append("**************************\n\n");
for(int i=0;i<qReg.length;i++){
QRegisterSegmentForAlu.getAluQreg().append("index:\t"+qReg[i].getIndex()+"\t"+
"value: \t"+qReg[i].getValue()+"\n");
} }
/** method to show content of QRegister after load instruction */
public static void showLoadQReg(){
Globals.getGui().getMainPane().getQRegisterDynamicsPane().getaluSegmentWindow();
QRegisterSegmentForLoad.getLoadQreg().append("**********************\n");
QRegisterSegmentForLoad.getLoadQreg().append(“ QUEUE REGISTER CONTENT AFTER LOAD OPERATION \n");
QRegisterSegmentForLoad.getLoadQreg().append("************************\n\n");
for(int i=0;i<qReg.length;i++){
QRegisterSegmentForLoad.getLoadQreg().append("index:\t"+qReg[i].getIndex()+"\t"+
"value: \t"+qReg[i].getValue()+"\n");
} }
/** method to return a value at particular index of the QRegister*/
public static int getIndexValue(int index){
return qReg[index].getValue();
}
/** check if queue is full */
public boolean isFull(){
if(qMaxSize==size()){
return true;
} else
return false;
}
/**check for empty queue */
public boolean isEmpty(){
if (qReg[QH]==null){
return true;
} else
return false;
}
/** enqueue a value at the QT*/
public static void enqueue(int value){
qReg[QT].setValue(value);
QT=(QT+1)%qReg.length;
qSize++;
}
/** dequeue a value at QH*/
public static int dequeue(){
int consume=getQHValue();
QH=(QH+1)%qReg.length;
return consume;
}
/**method to store a value at a particular index */
public static void setStoreValue(int val){
int index=(QH)+val;
int regIndx;
if(index<0){
JOptionPane.showMessageDialog(null, "Offset index is out of range");
} else{
int head=dequeue();
for(int i=0;i<qReg.length;i++){
regIndx=qReg[i].getIndex();
if(regIndx==index){
qReg[i].setValue(head);
} }
} }
/** method to get offset index*/
public static int getOffsetIndex(int val){
int index=(QH)+val;
return index;
}
/** method for getting offset value*/
public static int getOffsetValue(int j){
int offsetIndex=(QH-1)+j;
if(offsetIndex<0){
JOptionPane.showMessageDialog(null, "Offset index is out of range");
return 0;
} else{
int offsetValue=getIndexValue(offsetIndex);
QH=(QH+1)%qReg.length;
return offsetValue;
} }
/** method to return the current size of the QRegister*/
public int size(){
return (qMaxSize-QH+QT)%qMaxSize;
}
public int qLength(){
return qMaxSize;
}
/** get number of consume data*/
public static int getConsumeData(){
return CN;
}
/** get number of produce data*/
public static int getProduceData(){
return PN;
}
/** method to return current Queue Tail Index*/
public static int getQT(){
return QT;
}
/** Method to return current Queue Head Index*/
public int getQH(){
return QH;
}
/** method to set QT value */
public void setQTValue(int val){
qReg[QT].setValue(val);
}
/**Method to return the value of Queue Head*/
public static int getQHValue(){
int value=qReg[QH].getValue();
CN++;
return value;
}
/**Method to get current Queue Tail value */
public int getQTValue(){
int val=qReg[QT-1].getValue();
return val;
}
/**Method to reset the Queue Register values to zero (0) */
public static void clearReg(){
for(int i=0;i<qReg.length;i++){
qReg[i].setValue(0) ; }
}
/**Method to update the QRegiste value to a given value */
public static void updateQRegister(int index, int val){
qReg[index].setValue(val);
}
/** Method For returning the set of QRegisters.*/
public static QRegister[]getQRegister(){
return qReg;
}
/** Method to reinitialize the values of the QRegisters**/
public static void resetQRegisters(){
for(int i=0; i< qReg.length; i++){
qReg[i].resetValue();
} }
/** Each individual QRegister is a separate object and Observable. This method * adds the given Observer to each one */
public static void addRegistersObserver(Observer observer) { for (int i=0; i<qReg.length; i++) {
qReg[i].addObserver(observer);
} }
/** Each individual register is a separate object and Observable. This handy method * will delete the given Observer from each one. Currently does not apply to Program * Counter */
public static void deleteRegistersObserver(Observer observer) { for (int i=0; i<qReg.length; i++) {
qReg[i].deleteObserver(observer);
} }
}
QInstructionSet.JAVA CLASS package qsim.registers;
import javax.swing.JOptionPane;
import qsim.*;
/** The list of Instruction objects, each of which represents a QC instruction */
public class QInstructionSet{
/***************************************************************/
/** list of implemented Queue Core Instruction Set Architecture*/
/***************************************************************/
/*********/
/** ld **/
/** st **/
/** add **/
/** sub **/
/** mul **/
/** div **/
/** mod **/
/** and **/
/** or **/
/** xor **/
/*********/
/**method for performing load operation */
public static void load(int val){
QRegisterFile.enqueue(val);
}
/** method for performing store operation */
public static void store(int value){
int index= QRegisterFile.getOffsetIndex(value);
int storeValue= QRegisterFile.getQHValue();
QRegisterFile.setStoreValue(value);
Globals.getGui().getResultsPane().getResultsTextArea().append("\n RESULS OF 'STORE' OPERATION " +"\n---\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("THE VALUE
"+storeValue+" WAS SUCCESSFULLY STORED AT INDEX "+index +"\n" );
}
/** method for performing addition operation*/
public static void addition(int offset){
int src1=QRegisterFile.dequeue();
int src2=QRegisterFile.getOffsetValue(offset);
int sum=src1+src2;
Globals.getGui().getResultsPane().getResultsTextArea().append("\n RESULS OF 'ADDITION' OPERATION " +"\n---\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF QH [SRC1 ]= "+src1+"\n" );
Globals.getGui().getResultsPane().getResultsTextArea().append("OFFSET VALUE=
"+offset +"\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF QH+OFFSET[SRC2]= "+src2 +"\n");
QRegisterFile.enqueue(sum);
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE of THE OPERATION: ADD " +offset+" = "+sum+"\n");
}
/** method for performing subtraction operation */
public static void subtract(int offset){
int src1=QRegisterFile.dequeue();
int src2=QRegisterFile.getOffsetValue(offset);
int diff=src1-src2;
Globals.getGui().getResultsPane().getResultsTextArea().append("\n RESULS OF 'SUBTRACTION' OPERATION " +"\n---\n\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF QH [SRC1 ]= "+src1+"\n\n" );
Globals.getGui().getResultsPane().getResultsTextArea().append("OFFSET VALUE=
"+offset +"\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF QH+OFFSET[SRC2]= "+src2 +"\n");
QRegisterFile.enqueue(diff);
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE of THE OPERATION: SUB " +offset+" = "+diff+"\n");
}
/** method for performing multiplication operation*/
public static void multiply(int offset){
int src1=QRegisterFile.dequeue();
int src2=QRegisterFile.getOffsetValue(offset);
int prod=src1*src2;
Globals.getGui().getResultsPane().getResultsTextArea().append("\n RESULS OF 'MULTIPLICATION' OPERATION " +"\n---\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF QH [SRC1 ]= "+src1+"\n" );
Globals.getGui().getResultsPane().getResultsTextArea().append("OFFSET VALUE=
"+offset +"\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF QH+OFFSET[SRC2]= "+src2 +"\n");
QRegisterFile.enqueue(prod);
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE of THE OPERATION: MUL " +offset+" = "+prod+"\n");
}
/** method for performing modulo arithmetic operation*/
public static void modulo(int offset){
int src1=QRegisterFile.dequeue();
int src2=QRegisterFile.getOffsetValue(offset);
if(src2==0){
JOptionPane.showMessageDialog(null, " CANNOT DIVIDE BY ZERO:
UNSUCCESSFUL MODULO OPERATION !!!");
} else{
int mod=src1%src2;
Globals.getGui().getResultsPane().getResultsTextArea().append("\n RESULS OF 'MODULO' OPERATION " +"\n---\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF QH [SRC1 ]= "+src1+"\n" );
Globals.getGui().getResultsPane().getResultsTextArea().append("OFFSET VALUE=
"+offset +"\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF QH+OFFSET[SRC2]= "+src2 +"\n");
QRegisterFile.enqueue(mod);
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE of THE OPERATION: MOD " +offset+" = "+mod+"\n");
}
}
/** method for performing division operation*/
public static void division(int offset){
int src1=QRegisterFile.dequeue();
int src2=QRegisterFile.getOffsetValue(offset);
if(src2==0){
JOptionPane.showMessageDialog(null, "CANNOT DIVIDE BY ZERO:
UNSUCCESSFUL DIVISION OPERATION !!!");
}
else{
double div=src1/src2;
QRegisterFile.enqueue((int)div);
Globals.getGui().getResultsPane().getResultsTextArea().append("\n RESULS OF 'DIVISION' OPERATION " +"\n---\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF QH [SRC1 ]= "+src1+"\n" );
Globals.getGui().getResultsPane().getResultsTextArea().append("OFFSET VALUE=
"+offset +"\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF QH+OFFSET[SRC2]= "+src2 +"\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF THE OPERATION: DIV " +offset+" = "+div+"\n");
}
}
/** method for performing bitwise AND operation*/
public static void and(int offset){
int src1=QRegisterFile.dequeue();
int src2=QRegisterFile.getOffsetValue(offset);
int and=src1&src2;
QRegisterFile.enqueue(and);
Globals.getGui().getResultsPane().getResultsTextArea().append("\n RESULS OF BITWISE 'AND' OPERATION " +"\n---\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF QH [SRC1 ]= "+src1+"\n" );
Globals.getGui().getResultsPane().getResultsTextArea().append("OFFSET VALUE=
"+offset +"\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF QH+OFFSET[SRC2]= "+src2 +"\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF THE OPERATION: AND " +offset+" = "+and+"\n");
}
/** method for performing bitwise OR operation*/
public static void or(int offset){
int src1=QRegisterFile.dequeue();
int src2=QRegisterFile.getOffsetValue(offset);
int or=src1|src2;
QRegisterFile.enqueue(or);
Globals.getGui().getResultsPane().getResultsTextArea().append("\n RESULS OF BITWISE 'OR' OPERATION " +"\n---\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF QH [SRC1 ]= "+src1+"\n" );
Globals.getGui().getResultsPane().getResultsTextArea().append("OFFSET VALUE=
"+offset +"\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF QH+OFFSET[SRC2]= "+src2 +"\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF THE OPERATION: OR " +offset+" = "+or+"\n");
}
/** method for performing bitwise XOR operation*/
public static void xor(int offset){
int src1=QRegisterFile.dequeue();
int src2=QRegisterFile.getOffsetValue(offset);
int xor=src1^src2;
QRegisterFile.enqueue(xor);
Globals.getGui().getResultsPane().getResultsTextArea().append("\n RESULS OF BITWISE 'XOR' OPERATION " +\n---\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF QH [SRC1 ]= "+src1+"\n" );
Globals.getGui().getResultsPane().getResultsTextArea().append("OFFSET VALUE=
"+offset +"\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF QH+OFFSET[SRC2]= "+src2 +"\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF THE OPERATION: XOR " +offset+" = "+xor+"\n");
}
/** method for performing bitwise NOT operation*/
public static void not(int offset){
int src1=QRegisterFile.dequeue();
int src2=QRegisterFile.getOffsetValue(offset);
int not=~src2;
QRegisterFile.enqueue(not);
Globals.getGui().getResultsPane().getResultsTextArea().append("\n RESULS OF BITWISE 'NOT' OPERATION " +"\n---\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF QH [SRC1 ]= "+src1+"\n" );
Globals.getGui().getResultsPane().getResultsTextArea().append("OFFSET VALUE=
"+offset +"\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF QH+OFFSET[SRC2]= "+src2 +"\n");
Globals.getGui().getResultsPane().getResultsTextArea().append("VALUE OF THE OPERATION: NOT " +offset+" = "+not+"\n");
} }
QSIM PACKAGE QCprogram.JAVA CLASS
package qsim;
import java.util.*;
import java.io.*;
import qsim.registers.*;
/** Internal representations of QC program */
public class QCprogram {
private static String filename;
private static ArrayList sourceList;
private ArrayList tokenList;
private ArrayList parsedList;
private ArrayList machineList;
private String inst;
/** Generate list of source statements that comprise the program.
* @return ArrayList of String. Each String is one line of QC source code.
**/
public static ArrayList getSourceList() { return sourceList;
}
/** Produces name of associated source code file.
* @return File name as String.
**/
public static String getFilename() {