UNIT 2: CONTROL UNIT DESIGN/OPERATION
3.1 MICRO OPERATIONS
The prefix micro refers to the fact that each step is very simple and accomplishes very little. To design a control unit each of the smaller cycles involves a series of step each of which involves the processor registers. We refer to these steps as micro operations. Micro operations are the functional, or atomic operations of a processor.
Three. Now, we turn to the question of how these functions are performed or, more specifically, how the various elements of the processor are controlled to provide these functions. Thus, we turn to a discussion of the control unit, which controls the operation of the processor.
We have seen that the operation of a computer, in executing a program, consists of a sequence of instruction cycles, with one machine instruction per cycle. Of course, we must remember that this sequence of instruction cycles is not necessarily the same as the written sequence of instructions that make up the program, because of the existence of branching instructions. What we are referring to here is the execution time sequence of instructions.
We have further seen that each instruction cycle is made up of a number of smaller units. One subdivision that we found convenient is fetch, indirect, execute, and interrupt, with only fetch and execute cycles always occurring.
To design a control unit, however, we need to break down the description further. In our discussion of pipelining in Chapter 12, we began to see that a further decomposition is possible. In fact, we will see that each of the smaller cycles involves
a series of steps, each of which involves the processor registers. We will refer to these steps as micro-operations. The prefix micro refers to the fact that each step is very simple and accomplishes very little. Figure 15.1 depicts the relationship among the various concepts we have been discussing. To summarize, the execution of a program consists of the sequential execution of instructions. Each instruction is executed during an instruction cycle made up of shorter subcycles (e.g., fetch, indirect, execute, interrupt). The execution of each subcycle involves one or more shorter operations, that is, micro-operations.
Micro-operations are the functional, or atomic, operations of a processor.
In this section, we will. examine micro-operations to gain an understanding of how
the events of any instruction cycle can be described as a sequence of such m' operations. A simple example will be used. In the remainder of this chapter.
-then show how the concept of micro-operations serves as a guide to the desi=the control unit.
'We begin by looking at the fetch cycle, which occurs at the beginning of eac_- _struction cycle and causes an instruction to be fetched from memory.
For purp,: of discussion, we assume the organization depicted in Figure 12.6.
Four register• involved:
Memory address register (MAR): Is connected to the address lines of the tem bus. It specifies the address in memory for a read or write operation.
Memory buffer register (MBR): Is connected to the data lines of the system -- _ It contains the value to be stored in memory or the last value read from melr _ Program counter (PC): Holds the address of the next instruction to be fete==Instruction register (IR): Holds the last instruction fetched.
Let us look at the sequence of events for the fetch cycle from the poin_:
view of its effect on the processor registers. An example appears in Figure 15.-. .=_ the beginning of the fetch cycle, the address of the next instruction to be execs:.=-is in the program counter (PC); in this case, the address is 1100100. The first steto move that address to the memory address register
(MAR) because this is only register connected to the address lines of the system bus. The second step bring in the instruction. The desired address (in the MAR) is placed on the ad c== -
We have seen that the operation of a computer, in executing a program, consists of a sequence of instruction cycles, with one machine instruction per cycle. Of course, we must remember that this sequence of instruction cycles is not necessarily the same as the written sequence of instructions that make up the program, because of the existence of branching instructions. What we are referring to here is the execution time sequence of instructions.
We have further seen that each instruction cycle is made up of a number of smaller units.
One subdivision that we found convenient is fetch, indirect, execute, and interrupt, with only fetch and execute cycles always occurring.
To design a control unit, however, we need to break down the description further. In fact, we will see that each of the smaller cycles involves a series of steps, each of which involves the processor registers. We will refer to these steps as micro-operations. The prefix micro refers to the fact that each step is very simple and accomplishes very little. Figure 15.1 depicts the relationship among the various concepts we have been discussing. To summarize, the execution of a program consists of the sequential execution of instructions. Each instruction is executed during an instruction cycle made up of shorter subcycles (e.g., fetch, indirect, execute, interrupt). The execution of each subcycle involves one or more shorter operations, that is, micro-operations.
Micro-operations are the functional, or atomic, operations of a processor.
bus, the control unit issues a READ command on the control bus, and the result appears on the data bus and is copied into the memory buffer register (MBR). We also need to increment the PC by the instruction length to get ready for the next instruction. Because these two actions (read word from memory, increment PC) do not interfere with each other, we can do them simultaneously to save time. The third step is to move the contents of the MBR to the instruction register (IR). This frees up the MBR for use during a possible indirect cycle.
Thus, the simple fetch cycle actually consists of three steps and four microoperations. Each micro-operation involves the movement of data into or out of a register. So long as these movements do not interfere with one another, several of them can take place during one step, saving time.
Symbolically, we can write this sequence of events as follows:
t1: MAR E- (PC) t2: MBR <-- Memory PC <- (PC) + I t3: IR <-- (MBR) where I is the instruction length. We need to make several comments about this sequence. We assume that a clock is available for timing purposes and that it emits regularly spaced clock pulses. Each clock pulse defines a time unit. Thus, all time units are of equal duration. Each micro-operation can be performed within the time of a single time unit. The notation (ti, t2, t3) represents successive time units. In words, we have
I First time unit: Move contents of PC to MAR.
Second time unit: Move contents of memory location specified by MAR to MBR. Increment by I the contents of the PC.
Third time unit: Move contents of MBR to IR.
Note that the second and'third micro-operations both take place during the second time unit. The third micro-operation could have been grouped with the fourth without affecting the fetch operation:
t1: MAR <- (PC) t2: MBR <- Memory t3: PC E- (PC) + I IR <- (MBR) The groupings of micro-operations must follow two simple rules:
The proper sequence of events must be followed. Thus (MAR - (PC)) must precede (MBR - Memory) because the memory read operation makes use of the address in the MAR.
Conflicts must be avoided. One should not attempt to read to and write from the same register in one time unit, because the results would be unpredictable.
For example, the micro-operations (MBR ¢-- Memory) and (IR <- MBR) should not occur during the same time unit.
A final point worth noting is that one of the micro-operations involves an addition. To avoid duplication of circuitry, this addition could be performed by the ALU. The use of the ALU may involve additional micro-operations, depending on the functionality of the ALU and the organization of the processor. We defer a discussion of this point until later in this chapter.
It is useful to compare events described in this and the following subsections to Figure 3.5. Whereas micro-operations are ignored in that figure, this discussion shows the micro-operations needed to perform the subcycles of the instruction cycle.
Once an instruction is fetched, the next step is to fetch source operands.
Continuing our simple example, let us assume a one-address instruction format, with direct and indirect addressing allowed. If the instruction specifies an indirect address, then ar indirect cycle must precede the execute cycle. The data flow differs somewhat from_ that indicated in Figure 12.7 and includes the following micro-operations:
tl: MAR <-- (IR(Address)) t2: MBR F- Memory
t3: IR(Address) F- (MBR(Address))
The address field of the instruction is transferred to the MAR. This is then use to fetch the address of the operand. Finally, the address field of the IR is update from the MBR, so that it now contains a direct rather than an indirect address.
The IR is now in the same state as if indirect addressing had not been use and it is ready for the execute cycle. We skip that cycle for a moment, to consider t interrupt cycle.
At the completion of the execute cycle, a test is made to determine whether any- :-_abled interrupts have occurred. If so, the interrupt cycle occurs. The nature of cycle varies greatly from one machine to another. We present a very simple sequeof events, as illustrated in Figure 12.8. We have
t1: MBR E- (PC)
t2: MAR F- Save Address PC F- Routine Address t3: Memory E- (MBR)
In the first step, the contents of the PC are transferred to the MBR, so that u-can be saved for return from the interrupt. Then the MAR is loaded with the add- .at which the contents of the PC are to be saved, and the PC is loaded with the add to the MAR and PC, respectively. In any case, once this is done, the final step is to store the MBR, which contains the old value of the PC, into memory. The processor is now ready to begin the next instruction cycle.
The fetch, indirect, and interrupt cycles are simple and predictable. Each involves a small, fixed sequence of micro-operations and, in each case, the same micro-operations are repeated each time around.
This is not true of the execute cycle. Because of the variety opcodes, there are a number of different sequences of micro-operations that can occur. Let us consider several hypothetical examples.
First, consider an add instruction:
ADD R1, X
which adds the contents of the location X to register R1. The following sequence of micro-operations might occur:
We begin with the IR containing the ADD instruction. In the first step, the address portion of the IR is loaded into the MAR. Then the referenced memory
location is read. Finallv. the contents of RI and MBR are added by the ALLT.
Again. this
is a simplified example. Additional micro-operations may be required to extract the register reference from the IR and perhaps to stage the ALt' inputs or outputs in some intermediate registers.
Let us look at two more complex examples. A common instruction is incre-ment and skip if zero:
The content of location X is incremented by l. If the result is 0, the next instruction is skipped. A possible sequence of micro-operations is
ti: MAR <-- (IR(address)) t2: MBR- F- Memory
tz : MBR <-- (MBR) + 1
tu: Memory <- (MBR)
If ( (MBR) = 0) then (PC F - (PC) + I)
The new feature introduced here is the conditional action. The PC is incremented if (MBR) = 0. This test and action can be implemented as one micro-operation. Note also that this micro-operation can be performed during the same time unit during which the updated value in MBR is stored back to memory.
It is worth pondering the minimal nature of the control unit. The control unit is the engine that runs the entire computer. It does this based only on knowing the instructions to be executed and the nature of the results of arithmetic and logical operations (e.g., positive, overflow, etc.). It never gets to see the data being processed or the actual results produced. And it controls everything with a few control signals to points within the processor and a few control signals to the system bus.
INTERNAL PROCESSOR ORGANIZATION
Figure 15.5 indicates the use of a variety of data paths. The complexity of this type of organization should be clear. More typically, some sort of internal bus arrangement, as was suggested in Figure 12.2, will be used.
Using an internal processor bus, Figure 15.5 can be rearranged as shown in Figure 15.6. A single internal bus connects the ALU and all processor registers.
CPU with Internal Bus.
Gates and control signals are provided for movement of data onto and off the bus from each register. Additional control signals control data transfer to and from the system (external) bus and the operation of the ALU.
Two new registers, labeled Y and Z, have been added to the organization. These are needed for the proper operation of the ALU. When an operation involving two operands is performed, one can be obtained from the internal bus, but the other must be obtained from another source.
The AC could be used for this purpose, but this limits the flexibility of the system and would not work with a processor with multiple general-purpose registers. Register Y provides temporary storage for the other input. The ALU is a combinatorial circuit (see Chapter 20) with no internal storage.
Thus, when control signals activate an ALU function, the input to the ALU is transformed to the output. Thus, the output of the ALU cannot be directly connected to the bus, because this output would feed back to the input.
Register Z provides temporary output storage. With this arrangement, an operation to add a value from memory to the AC would have the following steps:
t1: MAR <-- (IR(address)) t2: MBR E- Memory
t3: Y <__ (MBR) t4: Z f- (AC) + (Y) ts: AC F- (Z)
Other organizations are possible, but, in general, some sort of internal bus or set of internal buses is used. The use of common data paths simplifies the interconnection layout and the control of the processor. Another practical reason for the use of an internal bus is to save space.
To illustrate some of the concepts introduced thus far in this chapter, let us consider the Intel 8085. Its organization is shown in Figure 15.7. Several key components that may not be self-explanatory are:
Incrementer/decrementer address latch: Logic that can add 1 to or subtract 1 from the contents of the stack pointer or program counter. This saves time by avoiding the use of the ALU for this purpose.
Interrupt control: This module handles multiple levels of interrupt signals.
Serial I/O control: This module interfaces to devices that communicate 1 bit at a time.
Table 15.2 describes the external signals into and out of the 8085. These are linked to the external system bus. These signals are the interface between the 8085 processor and the rest of the system (Figure 15.8).
The control unit is identified as having two components labeled (1) in; decoder and machine cycle encoding and (2) timing and control. A discuss"C _- - first component is deferred until the next section. The essence of the contthe timing and control module. This module includes a clock and accepts as i -current instruction and some external control signals. Its output consists C- : --signals to the other components of the processor plus control --signals to the :-_-system bus.
The timing of processor operations is synchronized by the clock trolled by the control unit with control signals. Each instruction cycle i, into from one to five machine cycles; each
machine cycle is in turn diNfrom three to five states. Each state lasts one clock cycle. During a state. the
son performs one or a set of simultaneous micro-operations as
determine
-control signals.
The number of machine cycles is fixed for a given instruction but one instruction to another. Machine cycles are defined to be equivalent cesses.
Thus, the number of machine cycles for an instruction depends on
bar of times the processor must communicate with external devices. For e an instruction consists of two 8-bit portions, then two machine, cycles are fetch the instruction. If that instruction involves a 1-byte memory or 1/0 then a third machine cycle is required for execution.
Figure 15.9 gives an example of 8085 timing, showing the value of external control signals. Of course, at the same time, the control unit generates internal control signals that control internal data transfers. The diagram shows the instruction cycle for an OUT instruction. Three machine cycles (Ml, M2, M3) are needed. During the first, the OUT instruction is fetched. The second machine cycle fetches the second half of the instruction, which contains the number of the 1/O device selected for output. During the third cycle, the contents of the AC are written out to the selected device over the data bus.
The Address Latch Enabled (ALE) pulse signals the start of each machine cycle from the control unit. The ALE pulse alerts external circuits.
During timing state T1 of machine cycle Mr, the control unit sets the IO/M signal to indicate that this is a memory operation. Also, the control unit causes the contents of the PC to be placed on the
addressed memory module places the contents of the addressed memory vocation on the address/data bus. The control unit sets the Read Control (RD) signal to indicate a read, but it waits until T3 to copy the data from the bus. This gives the memory module time to put the data on the bus and for the signal levels to stabilize. The final state, T4, is a bus idle state during which the processor decodes the instruction. The remaining machine cycles proceed in a similar fashion.
Finally, consider a subroutine call instruction. As an example, consider a branchand-save-address instruction:
BSA X
The address of the instruction that follows the BSA instruction is saved in location X, and execution continues at location X + I. The saved address will later be uses for return. This is a straightforward technique for providing subroutine calls. The fo=lowing micro-operations suffice:
t,: MAR E- (IR(address)) MBR ~- (PC)
tz: PC <-- (IR(address)) Memory <-- (MBR) t3: PC <__ (PC) + I
The address in the PC at the start of the instruction is the address of the nexinstruction in sequence. This is saved at the address designated in the IR.
The lateeaddress is also incremented to provide the address of the instruction for the next it - struction cycle.
We have seen that each phase of the instruction cycle can be decomposed into a sequence of elementary micro-operations. In our example, there is one sequence eac= for the fetch, indirect, and interrupt cycles, and, for the execute cycle, there is one sequence of micro-operations for each opcode.
To complete the picture, we need to tie sequences of micro-operations to-gether, and this is done in Figure 15.3. We assume a new 2-bit register called
the instruction cycle code (ICC). The ICC designates the state of the processor in terms of which portion of the cycle it is in:
00: Fetch 01: Indirect 10: Execute 11:
Interrupt
At the end of each of the four cycles, the ICC is set appropriately. The indirect cycle is always followed by the execute cycle. The interrupt cycle is always followed by the fetch cycle (see Figure 12.4). For both the fetch and execute cycles, the next cycle depends on the state of the system.
Thus, the flowchart of Figure 15.3 defines the complete sequence of microoperations, depending only on the instruction sequence and the interrupt pattern. Of course, this is a simplified example. The flowchart for an actual processor would be more complex. In any case, we have reached the point in our discussion in whic?, the operation of the processor is defined as the performance of a sequence of microoperations. We can now consider how the control unit causes this sequence to occur.
of tbp ~~r of the interrupt-processing routine. These two actions may each be - single micro-operation. However, because most processors provide multiple tyr_ and/or levels of interrupts, it may take one or more additional micro-operations obtain the Save Address and the Routine Address before they can be transfer the events of any instruction cycle can be described as a sequence of such micro operations. A simple example will be used. In the remainder of this chapter, we then show how the concept of micro-operations serves as a guide to the design of the control unit.